CMOS elements, i.e., complementary metal-oxide semiconductors, typically are employed in a complementary switch configuration commonly used as an inverter. However, the complementary switch configuration may equally be employed for other logic functions, for example, a NAND gate or the like. A large number of such CMOS inverters are usually implemented on a single semiconductor chip and a plurality of such chips may be used in a particular circuit arrangement. One such CMOS inverter configuration and an associated transmission gate form a CMOS device and are shown in FIG. 2 of the Drawing. As shown in FIG. 2, the inverter includes a p-channel MOSFET (metal oxide semiconductor field effect transistor) and a n-channel MOSFET.
It has been determined that during intervals in which an actual clock signal of appropriate magnitude and/or frequency is not being supplied to the CLOCK IN input of the CMOS device an indeterminate potential condition exists at the gate inputs of the MOSFETs. This indeterminate potential at the MOSFET gate inputs causes the p-channel MOSFET and the n-channel MOSFET to appear as short circuits thereby connecting the source of potential (+) from a regulated power supply (not shown) directly to a reference potential, in this example ground potential. This indeterminate potential condition may exist for all of the CMOS devices used in a particular circuit arrangement and usually occurs during power initialization of the circuit arrangement. The current demand on the regulated power supply created by the short circuit caused by many or all of the CMOS devices usually exceeds the current capacity of the power supply. Such a condition is commonly referred to as a surge current condition. Consequently, the power supply protective circuitry limits its output current which, in turn, causes the CMOS devices to remain inoperative. This condition obviously is undesirable. A simple solution to this problem could be to use a higher current capacity power supply. This is undesirable because of cost and size.